Digital Hardware Design

Verilator and C++ testbenches ⌗

• Verilator Pt.1: Introduction
• Verilator Pt.2: Basics of SystemVerilog verification using C++
• Verilator Pt.3: Traditional style verification example
• Verilator Pt.4: Modern transactional (UVM) style C++ testbench

Vivado Simulator Scripted Flow (Bash, Makefiles) ⌗

• Part I - Basic Vivado command-line tool usage
• Part II - Introduction to Bash scripting with Vivado tools
• Part III - Vivado Simulator flow using Makefiles